Google's Humufish TPU Bets on Intel's EMIB-T Packaging to Escape TSMC CoWoS Constraints
Google's next-generation TPU, codenamed Humufish, will use Intel's EMIB-T advanced packaging instead of the industry-standard TSMC CoWoS. EMIB-T offers scalability beyond reticle limits, lower cost, and better power delivery via through-silicon vias, but its manufacturing maturity at scale remains unproven.
A flagship AI accelerator moving off CoWoS to EMIB-T is architecturally compelling, but the transition's success hinges entirely on Intel's manufacturing execution.
Google's Humufish TPU is set to use Intel's EMIB-T packaging instead of TSMC CoWoS.
Nearly every leading AI training accelerator today is packaged on TSMC's CoWoS 2.5D flow.
CoWoS-S monolithic interposer is capped near 3.3x the reticle limit, which led TSMC to develop CoWoS-L; EMIB has no equivalent reticle-size constraint.
EMIB packaging is meaningfully cheaper than CoWoS because it eliminates the costly silicon interposer entirely.
Large CoWoS interposers waste wafer area at the edges and yield worse as they scale, while small EMIB bridges tile densely with little waste.
Adopting EMIB gives Google a second packaging source outside TSMC, reducing supply concentration risk.
Plain EMIB has shipped in volume for years, but EMIB-T is a new, unproven technology at manufacturing scale.
If Intel cannot ramp EMIB-T yield and volume on schedule, Google's fallback is the same capacity-constrained CoWoS supply this move was designed to avoid.
CoWoS places all dies on a single large silicon/RDL interposer; EMIB embeds small silicon bridges directly in the organic substrate only where die-to-die links are needed.
EMIB-T adds through-silicon vias (TSVs) to plain EMIB, routing power vertically through the bridge with added capacitors and a ground plane, enabling cleaner power delivery for next-gen HBM and higher-bandwidth interconnects.
โCompelling architecture. Execution is the question.โ
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